1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method of programming in the nonvolatile semiconductor memory device. More specifically, the present invention relates to a nonvolatile semiconductor memory device having a plurality of memory cells each of which can store a multi-level data, and a method of programming in the nonvolatile semiconductor memory device.
2. Description of the Related Art
Generally speaking, a nonvolatile semiconductor memory device such as a flash memory includes a plurality of memory cells each of which has a stacked gate structure (floating gate structure). That is to say, in a MOS transistor of the memory cell, a floating gate is provided between a substrate and a control gate. When charges are injected into the floating gate, a threshold value (threshold voltage) of each memory cell varies in accordance with the amount of the injected charges. In such a nonvolatile semiconductor memory device, the threshold voltages are correlated with data stored in the memory cell. Thus, by detecting the threshold voltage of each memory cell, the data stored in each memory cell can be read out.
A “programming” means an injection of the charges into a floating gate. In the programming of a memory cell, a predetermined potential is applied to source/drain, and a high potential is applied to a control gate of the memory cell. Accordingly, charges are injected into a floating gate of the memory cell. The programming may be performed for a plurality of memory cells by using one program pulse, which causes increase of a difference in the threshold voltage between a memory cell to which charges are injected at high-speed (high-efficiency) and a memory cell to which charges are injected at low-speed (low-efficiency). In order to prevent such a problem, a “verify (verifying step)” is generally carried out after the “programming”. In the verify, whether or not a desired amount of charges have been injected to the floating gate is checked. That is, in the verify, whether or not the threshold voltage of the memory cell have become a desired value.
FIG. 1 shows a relationship between a voltage Vcg applied to a control gate and a program time (the number of programming operations) when a memory cell is programmed according to a conventional programming method. In the conventional programming, as shown in FIG. 1, the voltage Vcg applied to the control gate of the memory cell is increases by ΔVcg as the number of programming operations increases. After every time the voltage is applied, a verify operation is performed to verify whether the threshold voltage of the memory cell has exceeded a predetermined value. With regard to the memory cell whose threshold voltage is determined by the verify operation to exceed the predetermined value, the programming is completed at that state. On the other hand, with regard to the memory cell whose threshold voltage is not determined to exceed the predetermined value, the programming operation continues until the threshold voltage reaches the predetermined value.
FIG. 2 shows a threshold voltage distribution with respect to the plurality of memory cells which are programmed according to the above-mentioned conventional method. The threshold voltage Vth is represented in the ordinate, and the number of memory cells is represented in the abscissa. A width ΔVth of the threshold voltage distribution represents the difference in the threshold voltage among the plurality of memory cells. That is, the threshold voltage Vth of each memory cell is in a range from the predetermined value Vref to Vref+ΔVth. Since the voltage of the program pulse is increased by ΔVcg according to the above-mentioned conventional programming, the width ΔVth is in proportion to ΔVcg.
In such a nonvolatile semiconductor memory device, the threshold voltages are correlated with the data stored in the memory cell. For example, each memory cell is programmed such that the data “0” corresponds to the higher threshold value and the data “1” corresponds to the lower threshold value.
Also, a multi-level storing technique is known as a technique for increasing the storage density in a nonvolatile semiconductor memory device. According to the multi-level storing technique, data of at least two bits can be stored in a single memory cell. Such a memory cell is called as an MLC (Multi-Level Cell). For example, in a four-level nonvolatile semiconductor memory device, a four-level memory cell can store 2-bit data “00”, “01”, “10” and “11”. Each memory cell is programmed to have a threshold voltage corresponding to any one of the “00”, “01”, “10” and “11” in accordance with the programmed data.
According to the multi-level (multi-bit) nonvolatile semiconductor memory device, two adjacent threshold voltage distributions corresponding to different storage data are close to each other as compared with a two-value (single-bit) nonvolatile semiconductor memory device. The narrower margin can cause a read error and hence deterioration of reading accuracy. As such, it is required to reduce the distribution width ΔVth with regard to the threshold voltages of the memory cells shown in FIG. 2 as possible. In the programming shown in FIG. 1, the program pulse increment ΔVcg may be set to a smaller value for the purpose of narrowing the distribution width ΔVth and widening the margin. In this case, however, there are problems in that the number of programming operations increases and hence the time necessary for the programming increases.
A technique for reducing the time required for the programming and for narrowing the distribution width is disclosed in Japanese Unexamined Patent Publication No. 2001-357693 (Patent Document No. 1). FIG. 3 shows a relationship between a voltage Vcg applied to a control gate and a program time (the number of programming operations) when a memory cell is programmed according to the method described in the Patent Document No. 1. According to the method, the programming operation is classified into a coarse stage and a fine stage. The programming in the coarse stage is performed until a threshold voltage of a memory cell exceeds a first reference level (Vref3) while incrementing the program voltage by ΔVcg3. The programming in the fine stage is performed until the threshold voltage of the memory cell exceeds a second reference level (Vref4) while incrementing the program voltage by ΔVcg4. The increment width ΔVcg4 of the program pulse in the fine stage is set smaller than the increment width ΔVcg3 of the program pulse in the coarse stage.
FIG. 4 shows a threshold voltage distribution just after the coarse stage and a threshold voltage distribution just after the fine stage. It is described in the above-referenced Patent Document No. 1 that the first reference value (level) Vref3 is preferably set to a value obtained by subtracting a value more than the increment width ΔVcg3 in the coarse stage from the second reference value (level) Vref4. A distribution width ΔVth3 of the threshold voltage distribution after the completion of the coarse stage is proportional to the increment width ΔVcg3. After the coarse stage, the programming in the fine stage is carried out. As a result, a final threshold voltage distribution is obtained as shown in FIG. 4, whose width ΔVth4 is proportional to the increment width ΔVcg4. The final distribution width ΔVth4 obtained after the fine stage is narrower than the distribution width ΔVth3 obtained just after the coarse stage, as shown in FIG. 4.
According to the conventional technique, as described above, the plurality of program pulses are used and successively applied in the programming (see FIGS. 1 and 3). Whether the threshold voltage exceeds the reference value Vref (see FIG. 2) or not is checked in the verifying operation. Thus, the post-programming threshold voltage is controlled to be a desired threshold voltage level. However, the reference value Vref can fluctuate due to influences of noises. In this case, as shown in FIG. 5, the threshold voltages of a part of the memory cells remain lower than the reference value Vref, and hence the final threshold voltage distribution expands to the lower side with regard to the threshold voltage. Such a problem can also occur in the case of the above-mentioned Patent Document No. 1. In other words, the final threshold voltage distribution after the fine stage expands to below the desired reference level Vref4.